The present invention relates in general to trench semiconductor devices and, more particularly, to methods of forming trenches in a semiconductor devices.
Trench semiconductor devices are used in many applications including power supplies, battery chargers, computers, and cell phones. During the process used to manufacture trench semiconductor devices a dry silicon etch step is used to form the trenches in a silicon material of the semiconductor device. However, the channel region inside the trench wall of the semiconductor device is frequently damaged and rough edges can be formed after the dry silicon etch step. The damage to the channel region can cause leakage which then causes reduced carrier lifetime in the channel area. Decreased carrier lifetime increases the voltage threshold thereby increasing the on-state resistance of the semiconductor device. There is conventional prior art cleaning processes used to reduce the damage to the trench wall of the semiconductor device, but is at the cost of extra process steps. However, the extra process steps used to remove the damage to the trench walls frequently does not completely anneal the trench walls leaving the damage to the channel region in the semiconductor device.
Furthermore, the trench depth of a semiconductor device is typically a critical dimension which is difficult to meet using the dry silicon etch process. or example, a trench power MOSFET device should have the trench depth just below the diffused body region to minimize the gate to drain capacitance and minimize the gate oxide electric field strength.
Accordingly, it is desirable to have a manufacturing process to form trenches in a semiconductor device without causing damage to the trench. Further, it is desirable to have the manufacturing process provide an accurate alignment of the trench bottom to specific dopant distribution during the process steps. The invention disclosed herein will address the above problems.